TY  - JOUR
T1  - An Efficient 1-Bit Full Subtractor Circuit Using Hybrid CMOS Logic
AU - Vignesh, O. AU - Mangalam, H. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 16
SP  - 2948
EP  - 2953
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.2948.2953
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.2948.2953
KW  - Full subtractor
KW  -low power
KW  -PTL
KW  -CMOS VLSI
KW  -multiplexer
KW  -XOR
AB  - The 1-bit full subtractor circuit plays the vital role in the design of arithmetic circuits. Full adder also acts as full subtractor when, we change all the inputs to complemented but here, we created a new low power single bit 8T full subtractor circuit where the only subtractor is needed. There are three parts used to design the full subtractor. That are passtransistor logic, 2T multiplexer and 3T XOR. It is a hardware efficient full subtractor circuit with a minimum number of MOS transistor counts that reduces the cruel problem of power. It also naturally reduces the delay of the overall circuit. The expexted simulation result of the proposed circuit has less power, the small size of chip area and high speed compared to 14, 15 and 16T full subtractor. The simulation result has been taken from Microwind 3.5 EDA tool on BSIM4 (advanced) 65nm technology at 0.7v supply voltage.
ER  -