TY  - JOUR
T1  - Performance Analysis of Low Power Port Bandwidth Weight Router Architecture
AU - Deivakani, M. AU - Shanthi, D. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 2
SP  - 277
EP  - 282
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.277.282
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.277.282
KW  - Error control
KW  -NoC
KW  -packetization
KW  -router architecture
KW  -routing techniques
AB  - Routers are playing crucial role in the field of networking. In this study, the multi port network on-chip router is proposed. The port weight based routing methodology is proposed in this study for low power applications. The proposed network architecture employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The proposed router does not maintain any routing table to route the packets from source to destination. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project navigator for synthesis purposes.
ER  -