TY  - JOUR
T1  - Comparative Analysis of Low Power Full Adders and 4x4 Vedic Multipliers
AU - Raman, Naveen 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 14
SP  - 2347
EP  - 2354
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.2347.2354
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.2347.2354
KW  - Full adder
KW  -Vedic multiplier
KW  -power consumption
KW  -digital signal processor
KW  -CMOS
AB  - The design of low power multipliers is the basic necessity for the design and the implementation of efficient power aware devices. Multipliers play a major role in digital signal processing applications. In multiplication, reliability is strongly affected by power consumption. Here Vedic multiplier is designed by the principles of Vedic Mathematics which is the ancient Indian system of mathematics. In this study four 4x4 Vedic multipliers are designed based on four different logic full adders such as 28T, TGFA, 14T and 16T. These multipliers and full adders were designed and simulated using microwind 2 electronic design automation tool with 0.12 μm technology. Finally a comparison is made on the performance of full adders and Vedic multipliers based on power consumption and transistor count.
ER  -