TY  - JOUR
T1  - Scheduled Progressive Edge Growth LDPC Encoder with Minimum Trapping Set
AU - Anand, A. AU - Senthilkumar, P. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 13
SP  - 2162
EP  - 2166
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.2162.2166
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.2162.2166
KW  - Scheduled PEG
KW  -density evolution
KW  -minimum trapping set
KW  -error floor
KW  -India
AB  - Outstanding bit error rate LDPC design in waterfall region and error floor region is one of the challenging tasks for the past decade. In this study, we focus the design of LDPC encoder with low the error floor and waterfall region of BER with minimum trapping set Scheduled Progressive Edge Growth (SPEG) LDPC encoder innovatively, the simulation result of density evolution and exit chart give the better convergence of LDPC encoder, BER performance in error floor can controlled by minimum trapping set and waterfall region controlled by scheduled PEG LDPC encoder with (1000, 500) with code length (n) is <600. The girth of the SPEG encoder is 8. SPEG with minimum trapping set will perform well for short length code also and it converges faster than the other PEG encoder.
ER  -