TY  - JOUR
T1  - Reducing Power and Delay in Instruction Queue for Sram Based Processor Unit
AU - Dhanalakshmi, G. AU - Sundarambal, M. AU - Muralidharan, K. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 11
SP  - 1785
EP  - 1790
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.1785.1790
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.1785.1790
KW  - Instruction queue
KW  -leakage power
KW  -dynamic power
KW  -CAM
KW  -SRAM
KW  -issue width
KW  -sensing delay
AB  - The ever-growing requirements of advanced computing platform are the extension of battery lifetime for high performance microprocessors. Power minimization has become a primary concern in microprocessor design. One of the main dynamic instruction scheduling used in data path designs is Instruction Queue (IQ) which allows the out of order execution in a superscalar processor. The Instruction Queue holds decoded and renamed instructions until they issue out-of-order to appropriate functional units. It consumes the considerable amount of power in a high performance processor and this unit is responsible for 27% of total chip power dissipation in typical superscalar microprocessor. The proposed technique aims at reducing the dynamic and static power dissipation in the Instruction Queue (IQ) by using power-gated match-line sense amplifier. It also reduces sensing delay during search operation in the IQ compared to conventional IQ. The proposed design of IQ using power gated match line sense amplifier is less hardware modifiable with the least amount of redesign and verification efforts, lowest possible design risk, least hardware overhead and without significant impact on the performance.
ER  -