TY  - JOUR
T1  - Design of an Error Tolerance Flip-Flop for Pipeline Architecture for SOC
AU - Raja, K. AU - Saravanan, S. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 11
SP  - 1686
EP  - 1690
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.1686.1690
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.1686.1690
KW  - EDCF
KW  -flip flop
KW  -pipelining
KW  -timing errors
KW  -error detection and correction
AB  - The study presents a error tolerant Flip-Flop design for pipeline Architecture for SOC. The proposed design uses the Error Detection and Correction (EDC) technique to achieve the goal. The design is applicable to all pipeline architectures. The proposed research uses the pulse generator and metastability detector to design the error tolerant pipeline. Timing failures induce delayed responses at the outputs of combinational logic circuits which leads to timing error. The research proposes the timing dilation correction circuit like after error detection the evaluation time for the logic is automatically extended by a single clock cycle for error correction using correct and valid data stored in each Flip-Flop. The proposed Error Detection and Correction (EDC) circuit is implemented using a pulse generator, D-flipflop, Xor and Latch. The implementation is performed in The power analysis is done through LTSpice tool in PTM 90 nm technology.
ER  -