TY  - JOUR
T1  - Analysis and Design of Low Power All Digital Phase Locked Loop via Dynamic Logic-Phase Frequency Detector in a Standard 0.25-μm CMOS Technology
AU - Kumar, T.M. Sathish AU - Perisamy, P.S. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 8
SP  - 1370
EP  - 1381
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.1370.1381
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.1370.1381
KW  - All Digital Phase Locked Loop (ADPLL)
KW  -Time-to-Digital Converter (TDC)
KW  -vernier
KW  -delay latch
KW  -India
AB  - A low power design of All Digital Phase Locked Loop (ADPLL) have become more attractive. It has better programmability, testability, portability and stability on ADPLL various actions and has good noise immunity. All digital system clock generation digital phase locked loop instead of traditional analog PLL is widely studied. The proposed new dynamic logic- phase frequency detector extends the detection range and eliminates the polarity reversal issues and increasing the speed of locking range at the output. Note the comparison between the proposed phase error such as the design of low power clock and the feedback clock is divided power Consumption respectively. ADPLL design through a dynamic logic phase frequency detector and is fabricated in parallel DTC and consumed the associated power 1.75 and 8.16 mW, respectively from 1.8 volts of electricity.
ER  -