TY  - JOUR
T1  - New Design for FIR Filter with Optimization of Speed and Power Using ASIC
AU - Vijay, Parvatham AU - Rajendran, Prabakaran 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 6
SP  - 1090
EP  - 1097
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.1090.1097
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.1090.1097
KW  - Application specific Integrated circuits
KW  -discrete wavelet transform
KW  -flipping architecture
KW  -logical elements
KW  -image compression
KW  -constant coefficient multiplier
AB  - This study develops and demonstrates the optimization of frequency and power of proposed parallel, pipelined flipping architecture for image compression using 2-D Discrete Wavelet Transform (DWT). All the filters used in DWT such as alpha, beta, gamma and delta are computed in parallel manner. Last two filters give the output of low pass and high pass filter. Because of parallel processing of these filters, waiting for the results of first two filters is not required. Modified bough-wooley with pipelined constant co-efficient multiplier is used for signed multiplication. One level 2-D DWT with pipelining and without pipelining of FIR filters are designed and synthesized using design compiler with 0.18Fm process technology. Two level with pipelining and without pipelining is designed using this new structure as well. Synthesis results of design compiler show that the speed of proposed one level 2-D DWT is increased by 44 and 2.47% of power is decreased compared to existing architectures. Hardware cost, latency of proposed structure is reduced compared with existing structures. Computation time, number of multipliers and adders required for this filter is compared with various architectures.
ER  -