TY  - JOUR
T1  - Power Optimization Technique for VLSI Circuits Using Fine Grain Clock Controller at Leaf Nodes
AU - Vijayakumari, V. AU - Titus, T. Joby 
JO  - Asian Journal of Information Technology
VL  - 13
IS  - 2
SP  - 83
EP  - 88
PY  - 2014
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2014.83.88
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2014.83.88
KW  - Clock gating
KW  -fine grain architecture
KW  -optical interconnects
KW  -VLSI
KW  -chip
AB  - Due to dramatic increase in portable and battery operated 
  applications; low power consumption has become the necessity in order to prolong 
  battery life. In Very Large Scale Integration (VLSI) architecture, power consumption 
  is an important criterion that determines the cost effectiveness of end product 
  size. Field Programmable Gate Arrays (FPGAs) are widely used VLSI circuits that 
  can contain even complex system on single chip. Despite their design cost advantage 
  FPGAs impose large dynamic and static power consumption overheads. In this study 
  various design techniques for low power optimization are surveyed. Among them 
  the effective way to reduce dynamic power consumption is observed when introducing 
  fine grain clock gating techniques at leaf node of FPGA architecture. By using 
  the method dynamic power consumption has been reduced 30% at each leaf node 
  of clock network.
ER  -