TY  - JOUR
T1  - Memory Design Considerations for DDR-3 SDRAM
AU - , T. Balaji AU - , V. Palanisamy 
JO  - Asian Journal of Information Technology
VL  - 6
IS  - 6
SP  - 720
EP  - 725
PY  - 2007
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2007.720.725
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2007.720.725
KW  - DDR-3
KW  -flyby topology
KW  -leveling
KW  -ODT
KW  -ZQ calibration
KW  -memory design
AB  - The emerging DDR3 SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory) standard will extend the performance range of DDR memories considerably, while maintaining some amount of backward compatibility with the existing DDR2 memory standard. The design of DDR-3 was done using Verilog HDL. The new features in DDR3 build on the DDR2 SDRAM add logical improvements to increase system bandwidth (up to 1.6GB s <SUP>1</SUP>) and increases performance at low power. Furthermore, the supply voltage for the memory is reduced from 1.8 V for DDR2 to just 1.5 V for DDR3 targeting a workday equivalent of battery time. DDR3 has additional features which include a Master Reset pin, an 8-bit pre-fetch and ZQ calibration in order to improve performance and reliability. This study will provide the reader with a detailed understanding of the key design considerations for DDR3 SDRAM system.
ER  -