TY  - JOUR
T1  - An FPGA Based Implementation of CA-CFAR Processor
AU - , Thamir R. Saed AU - , Jawad K. Ali AU - , Ziad T. Yassen 
JO  - Asian Journal of Information Technology
VL  - 6
IS  - 4
SP  - 511
EP  - 514
PY  - 2007
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2007.511.514
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2007.511.514
KW  - CFAR
KW  -FPGA design
KW  -signal processing
AB  - In this study, a constant false alarm rate processor is investigated and a special focusing is devoted to the cell-average constant false alarm rate (CA-CFAR) processor. This processor is analyzed and its performance is estimated. An FPGA-based CA-CFAR processor has been implemented using Xilinx integrated circuit chip XC9600. The implemented processor using this technique has been tested with signals imbedded with different types of clutter and noise-alike signals. The implementation process and the processor response reflect how this digital tool is excellent due to its high reliability and flexibility.
ER  -