TY  - JOUR
T1  - A New Trend for CISC and RISC Architectures
AU - , Hasan Krad AU - , Aws Yousif Al-Taie 
JO  - Asian Journal of Information Technology
VL  - 6
IS  - 11
SP  - 1125
EP  - 1131
PY  - 2007
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2007.1125.1131
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2007.1125.1131
KW  - Computer architecture
KW  -RISC
KW  -CISC
KW  -CRISC
AB  - The comparative study between CISC (Complex Instruction Set Computer) and RISC (Reduce Instruction Set Computers) has been a well known research area for many years. In this study, we try to address the new trend of these two architectures, which is CRISC (Complex-Reduce Instruction Set Computer). We chose the Intel Core Duo processor, Intel`s most recent processor, to be the focus of our study. The Core Duo processor features is highlighted, focusing on pipelining stages, clock speed, number of transistors, Instruction Set Architecture (ISA) and the improvement in cache technology.
ER  -