TY  - JOUR
T1  - Design of Low Power Double Edge Triggered D Flip Flop
AU - , S. Kaja Mohideen AU - , J. Rajapaul Perinbam 
JO  - Asian Journal of Information Technology
VL  - 5
IS  - 10
SP  - 1113
EP  - 1116
PY  - 2006
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2006.1113.1116
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2006.1113.1116
KW  - Digital CMOS
KW  -double edge triggered flip flop
KW  -low power
KW  -low delay
KW  -VLSI
AB  - A double edge triggered flip flop latches data at both edges of clock and hence it is advantageous over single edge-triggered flip flop in terms of power consumption and operating speed. Design of a low power Double Edge Triggered D Flip Flop (DETDFF ) has been presented in this study and it is compared with two previously published DETDFFs for their performance and power consumption. The DETDFF circuits were simulated using TSPICE for 0.13 and 0.18µ technology CMOS process for different supply voltages. The proposed design is shown to have the lowest power consumption with respect to other double edge triggered flip-flops in all the above conditions.
ER  -