TY  - JOUR
T1  - Low-Power Pipeline FFT Processor with Area-efficient Multipliers
AU - , Jung-Yeol Oh AU - , Kwang-Ho Chun AU - , Myoung-Seob Lim 
JO  - Asian Journal of Information Technology
VL  - 4
IS  - 8
SP  - 768
EP  - 772
PY  - 2005
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2005.768.772
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2005.768.772
KW  - FFT
KW  -IFFT
KW  -wireless LAN
KW  -OFDM
KW  -DFT
KW  -pipeline architecture
AB  - Presented here a new efficient pipeline FFT(Fast Fourier Transform) architecture based on the radix-2 4 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multipliers can enhance the area/power efficiency of the design. From synthesis simulations, the proposed complex constant multiplier achieved above 60% area reduction compared with the conventional programmable multiplier.
ER  -