TY  - JOUR
T1  - Minimization of Reversible Adder Circuits
AU - , Saiful Islam AU - , Rafiqul Islam 
JO  - Asian Journal of Information Technology
VL  - 4
IS  - 12
SP  - 1146
EP  - 1151
PY  - 2005
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2005.1146.1151
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2005.1146.1151
KW  - Reversible logic
KW  -garbages
KW  -quantum costs
KW  -full adder
KW  -carry skip logic
AB  - Losing information causes losing power. Information is lost when the input vector cannot be uniquely recovered from the output vector of a combinational circuit. The input vector of reversible circuit can be uniquely recovered from the output vector. In this study we have emphasized on the design of reversible adder circuits that is efficient in terms of gate count, garbage outputs and quantum cost and that can be technologically mapped. It has been analyzed and demonstrated that the results of our proposed adder circuits shows better performance compared to similar type of existing designs. Technology independent equations required to evaluate these circuits have also been given.
ER  -