TY  - JOUR
T1  - Architectural Optimization and VLSI Implementation of CIKS Encryption Algorithm
AU - , N. Sklavos AU - , B. V. Izotov 
JO  - Asian Journal of Information Technology
VL  - 3
IS  - 11
SP  - 1159
EP  - 1169
PY  - 2004
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2004.1159.1169
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2004.1159.1169
KW  - 
AB  - Data Dependent Permutations (DDP) attracted the interest of cryptographers last years. CIKS-1 is a latest published block cipher based on DDP transformations. In this paper, an area optimized architecture and the FPGA implementation of this cipher are proposed. The proposed architecture introduces an area-optimized combination of the different encryption and decryption schemes of CIKS-1 algorithm. The comparisons of the introduced design with the conventional architecture prove that the proposed architecture allocates 20-30% less area and it is better by about 14% in the Area-Delay product. The Performance/Area ratio proves that the proposed architecture is superior to the conventional by about 25%. Detailed performance analysis results are presented. The proposed implementation is designed on a pipelined architecture and reaches throughput value up to 2.5 Gbps. The achieved high throughput ensures fast encryption and it is suitable for networks with hard performance demands.
ER  -