@article{MAKHILLIJSSCEA201710528810,
    title = {Design and Implementation of an Efficient FFT Processor using Modified Booth Multiplier},
    journal = {International Journal of System Signal Control and Engineering Application},
    volume = {10},
    number = {5},
    pages = {134-139},
    year = {2017},
    issn = {1997-5422},
    doi = {ijssceapp.2017.134.139},
    url = {https://makhillpublications.co/view-article.php?issn=1997-5422&doi=ijssceapp.2017.134.139},
    author = {A.,Aby and},
    keywords = {CSLA,modified booth,slices,LUT (look up tables),delays,PPG},
    abstract = {The FFT plays an important role in OFDM
regarding its performance. An efficient multiplier is
needed to perform butterfly operation in FFT. This
multiplier is related to area, power and time. The
performance of OFDM depends upon the multiplier. The
proposed multiplier is developed by using Verilog HDL
and implemented by using Model Sim 6.3c for stimulation
and Xilinx 12.4 for synthesis. The proposed multiplier
reduce the number of slices, LTU (look up tables) and
hence area and delay got reduced.}
    }