@article{MAKHILLIJSC20149521218,
    title = {ASIC Implementation of Low Power Area Efficient Folded Binary Comparator},
    journal = {International Journal of Soft Computing},
    volume = {9},
    number = {5},
    pages = {298-302},
    year = {2014},
    issn = {1816-9503},
    doi = {ijscomp.2014.298.302},
    url = {https://makhillpublications.co/view-article.php?issn=1816-9503&doi=ijscomp.2014.298.302},
    author = {N.,G.E. Kanya,A. and},
    keywords = {priority encoding,carry look ahead,tree structure,digital arithmetic,Binary comparator},
    abstract = {ASIC implementation of a parallel binary comparator based 
  on radix-2 tree structure, utilizing Carry Look Ahead (CLA) technique is proposed 
  in this study. This novel comparator architecture achieves both low power and 
  high-speed operation, particularly at low-input data activity environments. 
  The proposed comparator is designed using VHDL code and synthesized using ALTERA 
  QUARTUS-II. Experimental evaluation of the proposed and state of the art designs 
  revealed that the proposed comparator design exhibits a reduction in delay by 
  49.8% and gate count by 42.6% for a 16 bit design, compared to the best of the 
  schemes used for comparison.}
    }