@article{MAKHILLJEAS2018131716753,
    title = {Novel Eleven-Transistor (11T) SRAM for Low Power Consumption},
    journal = {Journal of Engineering and Applied Sciences},
    volume = {13},
    number = {17},
    pages = {7256-7259},
    year = {2018},
    issn = {1816-949x},
    doi = {jeasci.2018.7256.7259},
    url = {https://makhillpublications.co/view-article.php?issn=1816-949x&doi=jeasci.2018.7256.7259},
    author = {C.M.R.,D. Sharmila Devi,S. Kishen and},
    keywords = {SRAM,power consumption,access time,read/write,SNM,worse},
    abstract = {Low power SRAM array is fundamental to organize substantial reliability and prolonged battery life
for portable application. Since, charging/discharging enormous bit lines capacitance consume large portion of
power, new SRAM design is proposed to lessen the power consumption and access delay for read/write
operation. The proposed 11T cell contains two transistors in the feedback path of the respective inverter to
minimize the write power consumption. Cell is simulated in terms of speed, power and stability. The simulated
results show that the read and write power of the 11T SRAM cell is reduced up to 49 and 80% at 0.7 V,
respectively and cell achieves 2.5× higher Static Noise Margin (SNM) compared to the conventional 6T SRAM
cell. The designed cell can be utilized in mobile appliances even in worse temperature state with lower power
consumption.}
    }