@article{MAKHILLJEAS201813715961,
    title = {Analysis of DCVS and MODL Logic in CLA},
    journal = {Journal of Engineering and Applied Sciences},
    volume = {13},
    number = {7},
    pages = {1844-1850},
    year = {2018},
    issn = {1816-949x},
    doi = {jeasci.2018.1844.1850},
    url = {https://makhillpublications.co/view-article.php?issn=1816-949x&doi=jeasci.2018.1844.1850},
    author = {Nehru,Utlapalli Soma and},
    keywords = {low power VLSI,DCVS,MODL,MCC,CLA,CMOS logic},
    abstract = {This study deals about 4 bit carry look ahead adder implementation in differential cascade voltage
switch and multi output domino logic styles. The main idea of Manchester carry chain is splitting the carry into
odd and even parts for reducing the delay time for carry bit to increase the speed of the circuit. The DCVS and
MODL logic styles are analyzed in terms of power, delay and power delay product with supply
voltages 0.8-1.8 V and temperature 27°C at 180 nm technology.}
    }