@article{MAKHILLJEAS201813715962,
    title = {Design and Implementation of a Complex Binary Adder},
    journal = {Journal of Engineering and Applied Sciences},
    volume = {13},
    number = {7},
    pages = {1813-1828},
    year = {2018},
    issn = {1816-949x},
    doi = {jeasci.2018.1813.1828},
    url = {https://makhillpublications.co/view-article.php?issn=1816-949x&doi=jeasci.2018.1813.1828},
    author = {Tariq,H. and},
    keywords = {Binary complex numbers,FPGA,complex binary adder,Logism Software,microprocessors,utilizing},
    abstract = {To represent complex number as single-unit binary number, a complex binary number utilizing base
(-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based
on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex
FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2
binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion
that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today’s
microprocessors.}
    }