@article{MAKHILLJEAS20138913407,
    title = {Design of 4-Bit Memory Column Dram Cell in 0.18 μm CMOS Process},
    journal = {Journal of Engineering and Applied Sciences},
    volume = {8},
    number = {9},
    pages = {269-272},
    year = {2013},
    issn = {1816-949x},
    doi = {jeasci.2013.269.272},
    url = {https://makhillpublications.co/view-article.php?issn=1816-949x&doi=jeasci.2013.269.272},
    author = {Md.,Nasima,Labonnah F. and},
    keywords = {DRAM,4-bit memory column,3-transistor,DRAM cell,Malaysia},
    abstract = {A Dynamic Random Access Memories (DRAM) memory cell is a capacitor 
  that is charged to produce a 1 or a 0. Over the years, several different structures 
  have been used to create the memory cells on a chip. In today’s 
  technologies, the capacitive storage element of the memory cell is used to create 
  trenched filled with dielectric material. However to progress to the next generation 
  DRAM, all the major physical limitations like circuit complexity, longer read/write 
  times and delays of the 1-Transistor (1-T) and capacitor storage cell need to 
  overcome. In this research, a 4-bit memory column cell for DRAM is presented. 
  To design the column cell, 3-transistor DRAM is chosen as it is distinguished 
  from the one transistor cell to rely on a driver transistor. Moreover, the column 
  cell operates as a constant current source during the discharge of the bit-line. 
  CEDEC 0.18 μm CMOS process has been utilized to design the column cell. 
  Therefore, the simulated results show that the designed circuit has been operates 
  successfully to comply with the DRAM.}
    }