@article{MAKHILLAJIT20171666667,
    title = {FPGA Implementation of Area Efficient and High Throughput 2D DTCWT
Architecture with Pipelined Scheme},
    journal = {Asian Journal of Information Technology},
    volume = {16},
    number = {6},
    pages = {511-520},
    year = {2017},
    issn = {1682-3915},
    doi = {ajit.2017.511.520},
    url = {https://makhillpublications.co/view-article.php?issn=1682-3915&doi=ajit.2017.511.520},
    author = {Venkateshappa and},
    keywords = {Image compression,DTCWT,SPIHT,DWT,companding,FPGA},
    abstract = {Dual Tree Complex Discrete Wavelet Transform (DTCWT) decomposes input image into
approximation and six detail sub-bands using row and column processing filter banks. Each filter comprising
of 10 coefficients requires multipliers and adders that are twice larger than that of discrete wavelet transform
computation. In this study, the computation complexity in DTCWT computation is reduced by considering the
redundancy in filter coefficients. A multiplexer-demultiplexer based logic is designed to reduce the number of
filters by 75%, a pipeline architecture is designed to reduce the number multipliers by 60% as compared with
conventional DTCWT architecture. The designed architecture implemented on FPGA and the design operates
at frequency of >200 MHz.}
    }