@article{MAKHILLAJIT2005484964,
    title = {Low-Power Pipeline FFT Processor with Area-efficient Multipliers},
    journal = {Asian Journal of Information Technology},
    volume = {4},
    number = {8},
    pages = {768-772},
    year = {2005},
    issn = {1682-3915},
    doi = {ajit.2005.768.772},
    url = {https://makhillpublications.co/view-article.php?issn=1682-3915&doi=ajit.2005.768.772},
    author = {Jung-Yeol Oh,Kwang-Ho Chun and},
    keywords = {FFT,IFFT,wireless LAN,OFDM,DFT,pipeline architecture},
    abstract = {Presented here a new efficient pipeline FFT(Fast Fourier Transform) architecture based on the radix-2 4 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multipliers can enhance the area/power efficiency of the design. From synthesis simulations, the proposed complex constant multiplier achieved above 60% area reduction compared with the conventional programmable multiplier.}
    }