Thamir R. Saed  , Jawad K. Ali  , Ziad T. Yassen  , 
    An FPGA Based Implementation of CA-CFAR Processor,
    Asian Journal of Information Technology,
    Volume 6,Issue 4,
    2007,
    Pages 511-514,
    ISSN 1682-3915,
    ajit.2007.511.514,
    (https://makhillpublications.co/view-article.php?doi=ajit.2007.511.514)
    Abstract: In this study, a constant false alarm rate processor is investigated and a special focusing is devoted to the cell-average constant false alarm rate (CA-CFAR) processor. This processor is analyzed and its performance is estimated. An FPGA-based CA-CFAR processor has been implemented using Xilinx integrated circuit chip XC9600. The implemented processor using this technique has been tested with signals imbedded with different types of clutter and noise-alike signals. The implementation process and the processor response reflect how this digital tool is excellent due to its high reliability and flexibility.
    Keywords: CFAR;FPGA design;signal processing