Jung-Yeol Oh  , Kwang-Ho Chun  , Myoung-Seob Lim  , 
    Low-Power Pipeline FFT Processor with Area-efficient Multipliers,
    Asian Journal of Information Technology,
    Volume 4,Issue 8,
    2005,
    Pages 768-772,
    ISSN 1682-3915,
    ajit.2005.768.772,
    (https://makhillpublications.co/view-article.php?doi=ajit.2005.768.772)
    Abstract: Presented here a new efficient pipeline FFT(Fast Fourier Transform) architecture based on the radix-2 4 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multipliers can enhance the area/power efficiency of the design. From synthesis simulations, the proposed complex constant multiplier achieved above 60% area reduction compared with the conventional programmable multiplier.
    Keywords: FFT;IFFT;wireless LAN;OFDM;DFT;pipeline architecture