TY  - JOUR
T1  - An Enhanced Approach of Message Digest Scheme for FPGA
Based Sensor Node
AU - Saravanaselvan, A. AU - Paramasivan, B. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 22
SP  - 4571
EP  - 4577
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.4571.4577
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.4571.4577
KW  - Event driven architecture
KW  -FPGA
KW  -sensor node
KW  -security attacks
KW  -integrity
KW  -authentication
AB  - Most of the current sensor devices use general purpose processor which is not primarily designed
to offer the inherent parallelism for event-driven sensor applications. FPGA based event-driven architecture
can handle several events in parallel which removes the timing uncertainty and overhead. Due to random
deployment of sensor nodes in remote areas, nodes are vulnerable to many security attacks related to data
confidentiality, integrity and authentication. With respect to resource constraints of sensor nodes, traditional
security mechanisms are not suitable for wireless sensor nodes. Considering this, a message digest scheme by
using maximum length sequence primitive polynomial approach is presented for FPGA based event-driven
architecture so as to ensure node-level data integrity for time and mission critical tasks. In addition,
configurable serial transmitter and receiver blocks were added to the designed block using which data size can
be configured as per the application scenario. The performance of this scheme is evaluated and compared with
other existing processor-based schemes.
ER  -