TY  - JOUR
T1  - Implementation of Hybrid Vedic Multiplier Nikhilam Sutra and Karatsuba Algorithm for N-bit Multiplier Using Successive Approximation of N-1 Bit Multiplier
AU - Nisha Angeline, M. AU - Valarmathy, S. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 18
SP  - 3598
EP  - 3604
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.3598.3604
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.3598.3604
KW  - Nikhilam sutra
KW  -multiplication
KW  -numerical strength reduction
KW  -karatsuba algorithm
KW  -FPGA
AB  - Vedic mathematics is the technique to solve complex arithmetic computations. Using this technique,
complex problems can be solved easily. Normally, Urdhva Tiryakbhyam Sutra is generally known as Vedic
Multiplier. Nikhilam Sutra is a special case in Vedic Mathematics. But there is no proper implementation
hardware for Nikhilam Sutra for binary multiplication. The aim of this study is to design hardware for Nikhilam
Sutra using Karatsuba algorithm using successive approximation of N-1 bit multiplier. Multipliers are the basic
components used in many digital systems, digital signal processing operations and multimedia applications.
Digital multipliers are the major source of power dissipation. Multiplications are often implemented with
shift-and-add operations. In this study, we propose a method that combines the principles of Nikhilam sutra
and Karatsuba sutra for the multiplication of binary numbers. The calculation of remainder is based on Nikhilam
sutra using complement method and the weight reduction is carried out in the remainder by removing the MSB.
The numerical transformation of the numbers is done by Karatsuba algorithm. For the remainder multiplication,
only N-1 bit multiplier is required. Therefore, the algorithm requires only (N-1) x (N-1) bit multiplier for the
calculation remainder. By combining both algorithms, the number of multiplier is reduced and also the number
of bit for multiplier is also reduced. By applying this modification in the algorithm, strength of the multiplier is
reduced. The research is implemented in Xilinx vertex device. The power, area and delay are measured using
Cadence tool with 180 and 90nm technology. From the results’, the product of delay and area is reduced.
ER  -