TY  - JOUR
T1  - Design and FPGA Implementation of Bit Level Pipelined Digit Serial VLSI Architecture for a Viterbi Decoder
AU - Kalavathidevi, T. AU - Sakthivel, P. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 7
SP  - 1232
EP  - 1242
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.1232.1242
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.1232.1242
KW  - Power dissipation
KW  -digit size
KW  -Viterbi decoder
KW  -unfolding
KW  -bit level pipelining
AB  - This study addresses a systematic unfolding transformation technique to transform the conventional viterbi architecture to equivalent digit serial. The originality of the unfolding technique lies in the generation of functionally correct control circuits in digit serial architectures. Convolutional code is an essential Forward Error Correcting (FEC) code for many wireless communication systems. Viterbi decoder is an optimal algorithm for decoding a convolution code. Power dissipation is recognized as a critical parameter in modern Very Large Scale Integrated circuit (VLSI) design field. Viterbi decoder employed in digital wireless communication is complex and dissipates large power. The aim of the proposed method is to obtain high speed and low power Viterbi decoder using bit-level pipelined digit-serial architecture for various digit size and word length. In the digit-serial architecture N bits are processed per clock cycle and a word is processed per W/N clock cycles (W: word length, N: digit size). Bit-level pipelining technique is applied for each bit as well as for each block. Digit serial architecture and bit-level pipelining achieves high speed and low power. With this technique the viterbi decoder is designed for word length W = 8, 16, 32 and digit size N = 2, 4. The functionality is simulated and synthesized using Xilinx ISE 13.2i.
ER  -