N.  Saravanakumar, G.E. Kanya  Kumari, A.  Nandhakumar, A.  NirmalKumar, 
    ASIC Implementation of Low Power Area Efficient Folded Binary Comparator,
    International Journal of Soft Computing,
    Volume 9,Issue 5,
    2014,
    Pages 298-302,
    ISSN 1816-9503,
    ijscomp.2014.298.302,
    (https://makhillpublications.co/view-article.php?doi=ijscomp.2014.298.302)
    Abstract: ASIC implementation of a parallel binary comparator based 
  on radix-2 tree structure, utilizing Carry Look Ahead (CLA) technique is proposed 
  in this study. This novel comparator architecture achieves both low power and 
  high-speed operation, particularly at low-input data activity environments. 
  The proposed comparator is designed using VHDL code and synthesized using ALTERA 
  QUARTUS-II. Experimental evaluation of the proposed and state of the art designs 
  revealed that the proposed comparator design exhibits a reduction in delay by 
  49.8% and gate count by 42.6% for a 16 bit design, compared to the best of the 
  schemes used for comparison.
    Keywords: priority encoding;carry look ahead;tree structure;digital arithmetic;Binary comparator