M.  Deivakani, D.  Shanthi, 
    FPGA Based Adaptive Resource Efficient Error Control Methodology for Network on Chip,
    Research Journal of Applied Sciences,
    Volume 9,Issue 1,
    2014,
    Pages 48-52,
    ISSN 1815-932x,
    rjasci.2014.48.52,
    (https://makhillpublications.co/view-article.php?doi=rjasci.2014.48.52)
    Abstract: This research work proposes resource efficient and secured network on chip 
  router using error control schemes. The proposed method combines the Cipher 
  block encryption based parallel crossbar methodologies of the NoC data link 
  and network layers to efficiently gives error control strength in variable network 
  topology conditions. The proposed method significantly minimizes hardware utilization 
  when compared to other earlier research. This can be achieved by implementing 
  parallel cross bar architecture with Cipher block based ECC Coding Method in 
  NoC. The proposed system uses Modelsim Software for simulation purposes and 
  Xilinx Project Navigator for synthesis purposes.
    Keywords: Error control;cipher;data link;residual packet;interleaving