TY  - JOUR
T1  - Design and Optimization of a High Performance Low-Power CMOS Flex Cell
AU - Sreedevi, M. AU - Paul, P. Jeno 
JO  - International Journal of System Signal Control and Engineering Application
VL  - 3
IS  - 4
SP  - 65
EP  - 69
PY  - 2010
DA  - 2001/08/19
SN  - 1997-5422
DO  - ijssceapp.2010.65.69
UR  - https://makhillpublications.co/view-article.php?doi=ijssceapp.2010.65.69
KW  - Low-power
KW  -low-voltage
KW  -flex cells
KW  -voltaged
KW  -cells
KW  -India
AB  - A high performance low-power flex cell is being introduced. With increasing circuits’ complexity and demand to use portable devices, power consumption is one of the most important parameters these days. The close coupling between the clustering and mapping process is key to success of this design optimization technique. Specifically, the mapping process is tailored to choose from a variety of techniques that can be used to create new flex cells based upon the inputs, it receives from the clustering process. Such mapping techniques can include time-tested methods of gate sizing and transistor sizing as well as techniques typically found in manual design flows, e.g., creation of new transistor-level implementation of the function of a given cluster of standard cells. Simulation results are performed by HSPICE based on 0.18 μm CMOS technology shows that the new circuit has the lowest power-delay product over a wide range of voltages among several low-power flex cells of different CMOS logic styles.
ER  -