TY  - JOUR
T1  - Power Reduction in SRAM-Based Processor Units Using 7T HETTs
AU - Saravanan, S. AU - Kumar, V.M. Senthil AU - David, Aksa 
JO  - International Journal of Soft Computing
VL  - 10
IS  - 2
SP  - 211
EP  - 217
PY  - 2015
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2015.211.217
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2015.211.217
KW  - Heterojunctions
KW  -low power
KW  -processor
KW  -SRAM cells
KW  -tunneling transistor
AB  - In MOSFETs lower limit sub-threshold swing (60 mV/decade) restricts the low power operation. Low voltage operation is enabled by low threshold voltage while maintaining performance. Hence, steep sub-threshold slopes provide power-efficient operation without any loss of performance. To obtain sub-threshold swings of <30 mV/decade with large ON current, Si/SiGe heterojunction tunneling transistor uses gate controlled modulation. The sub-threshold swing of HETTs is <60 mV/decade. To overcome the impact of HETT characteristics on SRAM, seven transistors HETT based SRAM design is introduced. Without leakage-reduction techniques, it is now in the range of mA and in some cases can account for >50% of the total power consumption. Compared to CMOS this new HETT SRAM achieves reduction in leakage power. The obtained HETT, SRAM cells are used in register cells for power reduction in SRAM and CAM based processors. The average power consumption in 7T HETT SRAM is low as compared to 6T SRAM.
ER  -