TY  - JOUR
T1  - Clock Sharing Double Edge Triggered Flip Flop
AU - , C.N. Marimuthu AU - , Riboy Cheriyan AU - , P. Thangaraj 
JO  - International Journal of Soft Computing
VL  - 3
IS  - 5
SP  - 397
EP  - 402
PY  - 2008
DA  - 2001/08/19
SN  - 1816-9503
DO  - ijscomp.2008.397.402
UR  - https://makhillpublications.co/view-article.php?doi=ijscomp.2008.397.402
KW  - CMOS
KW  -clock branch sharing
KW  -low power
KW  -double edge
KW  -triggered
AB  - In very large scale integration, low power VLSI design is necessary to meet MOORE&#8217;S law and to produce consumer electronics with more back up and less weight. For a sequential circuit, most of the power consumption is due to clock signal required. It accounts for 30- 60% of the total power dissipation in a system. THE CLOCK system, which consists of the clock distribution network and timing elements, is one of the most power consuming components in a VLSI system. As a result, reducing the power consumed by flip-flops will have a great effect on the total power consumed. Voltage scaling is the most effective way to decrease power consumption, since power is proportional to the square of the voltage. However, voltage scaling is associated with threshold voltage scaling which can cause the leakage to increase exponentially. Besides supply voltage scaling, half of the power on the clock distribution network can be saved by using double-edge clocking. The power of the clocking system = P<SUB>clock_distribution_network </SUB>+ P<SUB>flip_flop</SUB>. Power consumption on the clock distribution network has been reduced to half by cutting the frequency of the clock by one half.
ER  -