@article{MAKHILLJEAS201914417427,
    title = {VLSI Implementation of Folded FIR Filter Structures Using
High Speed Multipliers},
    journal = {Journal of Engineering and Applied Sciences},
    volume = {14},
    number = {4},
    pages = {1070-1077},
    year = {2019},
    issn = {1816-949x},
    doi = {jeasci.2019.1070.1077},
    url = {https://makhillpublications.co/view-article.php?issn=1816-949x&doi=jeasci.2019.1070.1077},
    author = {S. and},
    keywords = {Finite Impulse Response (FIR),VLSI,design,complexity,linear prediction,bit-level},
    abstract = {Modern DSP systems are often well suited to VLSI implementation. Indeed, they are often technically
feasible or economically viable only if implemented using VLSI technologies. The purpose of designing special
purpose DSP systems is an interesting research topic but more important, it has significant industrial and
commercial relevance. Many DSP systems are produced in very large numbers and require high performance
circuits with respect to throughput and power consumption. A digital Finite Impulse Response (FIR) filter
performs the frequency shaping or the linear prediction on a discrete-time input sequence {x<sub>0</sub>, x<sub>1</sub>, -x<sub>2</sub>, ...}. The 
FIR filter is commonly used in many applications such as communication or multimedia signal processing. The
study is focused on the design of an efficient VLSI architecture for FIR filters which aims at reducing the power
consumption and also to reduce the hardware complexity. In the existing method, design of folded FIR filter
based on carry-save multiplier is presented. It does not allow the internal pipelining delays to be exploited. It
leads to significant increase in hardware as well as considerable increase in power consumption. It leads to less
throughput and increases hardware complexity. In the proposed method, design of folded Finite Impulse
Response (FIR) filters based on pipelined multiplier arrays is presented. The design is considered at the bit-level
and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware
complexity. Partially folded architectures are also proposed which are implemented by cascading a number of
folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a
straightforward implementation of a folded FIR filter based on the pipelined carry-save multiplier. The
comparison reveals that the proposed schemes may require 20-30% less hardware. Due to the lesser carry
propagation, the proposed method can achieve low power consumption and higher computational
speedstrategy.}
    }